/*
 * Copyright : (C) 2024 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK_UART_HW_H
#define RK_UART_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

/** @name Register Map
 *
 * Register offsets for the UART.
 */
#define RK_UART_RBR_OFFSET      0x0000U /* Receive Buffer Register */
#define RK_UART_DLL_OFFSET      0x0000U /* Divisor Latch Low */
#define RK_UART_THR_OFFSET      0x0000U /* Transmit Buffer Register */
#define RK_UART_DLH_OFFSET      0x0004U /* Divisor Latch High */
#define RK_UART_IER_OFFSET      0x0004U /* Interrupt Enable Register */
#define RK_UART_FCR_OFFSET      0x0008U /* FIFO Enable */
#define RK_UART_IIR_OFFSET      0x0008U /* Interrupt Identity Register */
#define RK_UART_LCR_OFFSET      0x000CU /* Line Control Register */
#define RK_UART_MCR_OFFSET      0x0010U /* Modem Control Register */
#define RK_UART_LSR_OFFSET      0x0014U /* Line Status Register */
#define RK_UART_MSR_OFFSET      0x0018U /* Modem Status Register */
#define RK_UART_SCR_OFFSET      0x001CU /* Scratchpad Register */
#define RK_UART_SRBR_OFFSET     0x0030U /* Shadow Receive Buffer Register */
#define RK_UART_STHR_OFFSET     0x0030U /* Shadow Transmit Holding Register */
#define RK_UART_FAR_OFFSET      0x0070U /* FIFO Access Register */
#define RK_UART_TFR_OFFSET      0x0074U /* Transmit FIFO Read */
#define RK_UART_RFR_OFFSET      0x0078U /* Receive FIFO write */
#define RK_UART_USR_OFFSET      0x007CU /* UART Status Register */
#define RK_UART_TFL_OFFSET      0x0080U /* Transmit FIFO level */
#define RK_UART_RFL_OFFSET      0x0084U /* Receive FIFO level */
#define RK_UART_SRR_OFFSET      0x0088U /* Software Reset Register */
#define RK_UART_SRTR_OFFSET     0x008CU /* Shadow Request to Send */
#define RK_UART_SBCR_OFFSET     0x0090U /* Shadow Break Control Register */
#define RK_UART_SDMAM_OFFSET    0x0094U /* Shadow DMA Mode */
#define RK_UART_SFE_OFFSET      0x0098U /* Shadow FIFO enable */
#define RK_UART_SRT_OFFSET      0x009CU /* Shadow RCVR Trigger */
#define RK_UART_STET_OFFSET     0x00A0U /* Shadow TX Empty Trigger */
#define RK_UART_HTX_OFFSET      0x00A4U /* Halt TX */
#define RK_UART_DMASA_OFFSET    0x00A8U /* DMA Software Acknowledge */
#define RK_UART_CPR_OFFSET      0x00F4U /* Component Parameter Register */
#define RK_UART_UCV_OFFSET      0x00F8U /* UART Component Version */
#define RK_UART_CTR_OFFSET      0x00FCU /* Component Type Register */

/** @name RK_UART_RBR_OFFSET Register
 */
#define RK_UART_RECV_DATA_MASK  0xFFU    /* Receive Data */

/** @name RK_UART_THR_OFFSET Register
 */
#define RK_UART_SEND_DATA_MASK  0xFFU   /* Send Data */

/** @name RK_UART_DLL_OFFSET Register
 */
#define RK_UART_DIV_LOWER_MASK  0xFFU   /* Baud Rate Divisor, lower 8 bits */

/** @name RK_UART_DLH_OFFSET Register
 */
#define RK_UART_DIV_UPPER_MASK  0xFFU   /* Baud Rate Divisor, upper 8 bits */

/** @name RK_UART_IER_OFFSET Register
 */
#define RK_UART_INTR_RX         (1U << 0) /* Receive interrupt enable bit */
#define RK_UART_INTR_TX_HOLD    (1U << 1) /* Send hold interrupt enable bit */
#define RK_UART_INTR_LINE       (1U << 2) /* Line status interrupt enable bit */
#define RK_UART_INTR_MODEM      (1U << 3) /* Modem status interrupt enable bit */
#define RK_UART_INTR_PROG       (1U << 3) /* Programmable interrupt enable bit */



/** @name RK_UART_LCR_OFFSET Register
 */
#define RK_UART_DATA_BITS       (3U << 0) /* Data length bits */
#define RK_UART_STOP_BIT        (1U << 2) /* Stop bits */
#define RK_UART_PARITY_ENABLE   (1U << 3) /* Parity enable bit */
#define RK_UART_EVEN_PARITY     (1U << 4) /* Even parity bit */
#define RK_UART_STICK_PARITY    (1U << 5) /* Stick parity bit */
#define RK_UART_BREAK_CONTROL   (1U << 6) /* Break control Bit */
#define RK_UART_DIVISOR_ENABLE  (1U << 7) /* Divisor latch access bit */


/** @name RK_UART_SRR_OFFSET Register
 */
#define RK_UART_RESET           (1U << 0) /* UART reset */
#define RK_UART_RCVR_FIFO_RESET (1U << 1) /* RCVR FIFO reset */
#define RK_UART_XMIT_FIFO_RESET (1U << 1) /* XMIT FIFO reset */



#ifdef __cplusplus
}
#endif

#endif /* RK_UART_HW_H */

